Jouni Isoaho

Analysis of delay variation in encoded on-chip bus signaling under process variation (2008)

VLSI Design

Tuuna S, Nigussie E, Isoaho J, Tenhunen H

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

AREA EFFICIENT DELAY-INSENSITIVE AND DIFFERENTIAL CURRENT SENSING ON-CHIP INTERCONNECT (2008)

2008 IEEE International SOC Conference

Nigussie E, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

High-performance long NoC link using delay-insensitive current-mode signaling (2007)

Ethiopia Nigussie, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, Jouni Isoaho

(Vertaisarvioitu alkuperäisartikkeli tai data-artikkeli tieteellisessä aikakauslehdessä (A1))

Current mode on-chip interconnect using level-encoded two-phase dual-rail encoding (2007)

2007 IEEE International Symposium on Circuits and Systems, IEEE International Symposium on Circuits and Systems. Proceedings

Nigussie E, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling (2006)

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures

Nigussie E, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

Analysis of crosstalk and process variations effects on on-chip interconnects (2006)

2006 International Symposium on System-on-Chip

Nigussie E, Tuuna S, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic (2006)

2006 IEEE International Symposium on Circuits and Systems, IEEE International Symposium on Circuits and Systems. Proceedings

Nigussie E, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

Reliable asynchronous links for SoC (2005)

2005 International Symposium on System-on-Chip

Nigussie E, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

On asynchronous full-duplex dual-rail link with multiple-valued current-mode signaling (2005)

2005 NORCHIP

Nigussie E, Plosila J, Isoaho J

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

Analyses of signaling techniques for self-timed systems (2004)

IEEE International Symposium on System-on-Chip

Ethiopia Nigussie, Johanna Tuominen, Jouni Isoaho

(Vertaisarvioitu artikkeli konferenssijulkaisussa (A4))

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Analysis of delay variation in encoded on-chip bus signaling under process variation (2008)

AREA EFFICIENT DELAY-INSENSITIVE AND DIFFERENTIAL CURRENT SENSING ON-CHIP INTERCONNECT (2008)

High-performance long NoC link using delay-insensitive current-mode signaling (2007)

Current mode on-chip interconnect using level-encoded two-phase dual-rail encoding (2007)

Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling (2006)

Analysis of crosstalk and process variations effects on on-chip interconnects (2006)

Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic (2006)

Reliable asynchronous links for SoC (2005)

On asynchronous full-duplex dual-rail link with multiple-valued current-mode signaling (2005)

Analyses of signaling techniques for self-timed systems (2004)